The present invention relates to an image sensor for use in an input section of a facsimile machine, etc. More particularly, it is directed to a manufacturing method of an image sensor in which light-receiving elements of a thin-film lamination structure are separated bit-by-bit. For instance, an image sensor in which a plurality of light-receiving elements are arranged in line with each light-receiving element consisting of a photodiode and a blocking diode connected back-to-back.
FIG. 7 shows an example of a conventional image sensor used in a facsimile machine, etc. to read images. A single light-receiving element 70 consists of a photodiode PD1 and a photodiode PD2 functioning as a blocking diode which are connected back-to-back. A plurality of such light-receiving elements 70 are arranged in line. The photodiodes PD1 and PD2 have a thin-film sandwiched structure in which a lower electrode (metal electrode) 72, a photoelectric conversion layer (a-Si (amorphous silicon) layer) 73 and an upper electrode (transparent electrode) 74 are sequentially formed on a substrate 71.
Referring to FIG. 8, a method of reading out signals from the above image sensor will be described below.
The photodiodes PD1 are scanned by a shift register SR so that pulses are sequentially applied thereto, and an electric charge is stored in each of the reverse-biased photodiodes PD1. If light is incident on a certain photodiode PD1 during one scan, an electric charge corresponding to the amount of incident light is discharged. Then, read pulses are sequentially applied from the shift resister SR to the photodiodes PD1, so that a charge corresponding to the discharge amount is stored again in the photodiode PD1. Image signals from the respective photodiodes PD1 are sequentially extracted by reading out a current produced by this re-charging via a read circuit 80. (refer to Japanese Patent Application Unexamined Publication No. Sho. 58-56363).
Since the photodiodes PD2 serve as switching diodes in the above reading method, it is preferred that they have a structure which allows a large forward current. It is thus more effective to provide an ohmic contact structure in which a doped a-Si layer 73a (see FIG. 7) is interposed between the metal electrode 72 and a non-doped a-Si layer 73b, rather than a Schottky structure in which the metal electrode 72 is in contact with a non-doped a-Si layer.
To provide such an ohmic contact structure, a conventional method involves the steps of depositing a metal film such as chromium (Cr) on the entire surface of the substrate 71; patterning the metal film by photolithography to form the lower electrode 72; depositing a doped a-Si film and a non-doped a-Si film sequentially; and patterning these deposited films by photolithography so as to form the doped a-Si layer 73a and the non-doped a-Si layer 73b.
However, according to this conventional manufacturing method, the doped a-Si layer 73a and the non-doped a-Si layer 73b are shaped into the same pattern as shown in FIG. 7. As a result, the doped a-Si layer 73a extends outside the area used for the photoelectric conversion. This outside area provides a large capacitance, resulting in a reduction of the detected output signal.
To make the size of the doped a-Si layer equal to that of the lower electrode 72, a method as shown in FIGS. 6(a)-6(g) has been proposed in which the following steps are sequentially performed. First, a chromium film 72' is deposited on a substrate 71 (FIG. 6(a)); the chromium film 72' is patterned to form a lower electrode 72 (FIG. 6(b)); a doped a-Si film 73a' is deposited (FIG. 6 (c) ; the doped a-Si film 73a' is patterned to form a doped a-Si layer 73a (FIG. 6(d)); a non-doped a-Si film 73b, and an indium tin oxide (ITO) film 74' are deposited (FIG. 6(e)); the non-doped a-Si film 73b, and the ITO film 74, are patterned to form a non-doped a-Si layer 73b and a transparent electrode 74 (FIG. 6(f)); and an insulating layer 75 is deposited and patterned, and a wiring metal film 76 is deposited and patterned (FIG. 6(g)).
However, even in this method, since the lower electrode 72 and the doped a-Si layer 73a are patterned by forming resist patterns by use of different masks, it may be the case that the lower electrode 72 and the doped a-Si layer 73a fail to have the same width due to mismatching of the masks. As a result, part of the doped a-Si layer 73a will be located outside the lower electrode 72 as shown in FIGS. 9(a) and 9(b), and will form a capacitor. This also causes an undesirable decrease in the detected output signal.
Further, to prevent the doped a-Si layer 73a from being formed outside the lower electrode 72, it may be conceivable to pattern the doped a-Si layer 73a into a smaller area than the lower electrode (FIG. 9(c)). However, this precludes the effective use of the lower electrode 72.